Traditional microprocessor designs typically utilize synchronous clocking techniques, which use a single clock phase that is globally distributed in an isochronous manner so that clock signal skew throughout the electronic package is minimized. Since all of the loads for this global clock are switched at roughly the same time, the simultaneous switching current demands placed on the package and the power distribution design typically will have a significant impact upon parameters or items such as performance, reliability, technology, wireability, yield and cost. The inductive effects that will occur with large switching currents may produce over and/or under voltage transients that contribute to premature failure of various electronic components. Such switching currents may also generate significant signal radiation requiring emission shielding to be incorporated in the electronic package.
Microprocessor chips incorporating a plurality of microprocessors can have a significantly larger number of simultaneous switch operations at a given time than do chips containing many other types of circuitry. Thus the above-referenced problems are particularly apparent in connection with microprocessor chips.
Additional information as to the operation of this invention in conjunction with a generalized switching current reduction application may be found in a co-pending application entitled “Multiphase Clocking Method and Apparatus” (Docket No. AUS920020470US1) filed concurrently herewith and incorporated herein by reference for all purposes. The referenced application names the same inventors and is assigned to the same assignee.
It would thus be desirable to reduce the switching current magnitude occurring at any given time and accordingly reduce inductive effects (L) and signal radiation generated with rapid current level changes (di/dt).